In the high speed USB field or a PCIe field, a data and clock recovery (CDR) circuit is usually applied to a receiver (Rx) of a physical layer (PHY). In the high speed physical layer, the CDR circuit is operated in several power modes. For example, these power modes include a normal mode, a max power-saving mode, a medium power-saving mode and a power off mode. Generally, in the high speed physical layer, the operation mode of the CDR circuit is switched between the normal mode and the power-saving mode.
In this context, the term “latency” of the CDR circuit indicates the wake up time from sleep. Generally, the CDR circuit has high latency when the operation mode of the CDR circuit is switched from the max power-saving mode to the normal mode, and the CDR circuit has low latency when the operation mode of the CDR circuit is switched from the medium power-saving mode to the normal mode.
FIG. 1 is a schematic functional block diagram illustrating the architecture of a conventional CDR circuit. As shown in FIG. 1, the CDR circuit 100 comprises a high speed phase detector 110, a charge pump 120, a voltage control oscillator (VCO) 130 and a frequency divider 140.
The high speed phase detector 110 receives a divided clock signal CLKd and a data signal Data. According to the result of comparing the divided clock signal CLKd with the data signal Data, the high speed phase detector 110 generates a phase difference signal Spd. According to the phase difference signal Spd, the charge pump 120 generates a control voltage Vctrl. According to the control voltage Vctrl, the voltage control oscillator 130 generates a recovered clock signal CLKr. The frequency divider 140 receives the recovered clock signal CLKr. After the frequency of the recovered clock signal CLKr is divided by N, the frequency divider 140 generates the divided clock signal CLKd.
Moreover, the charge pump 120 may be replaced by a counter. For example, the counter receives the phase difference signal Spd from the high speed phase detector 110. If the phase difference signal Spd is positive, the counting value is counted up. Whereas, if the phase difference signal Spd is negative, the counting value is counted down. According to the counting value, the counter generates the corresponding control voltage Vctrl and transmits the control voltage Vctrl to the voltage control oscillator 130.
For example, in the CDR circuit of FIG. 1, the frequency of the data signal Data is in the range between 1 GHz and 28 GHz. Since the data signal Data is transferred at a high data rate, the circuitry of the high speed phase detector 110 is complicated. For example, the high speed phase detector 110 is at least equipped with a sense amplifier, a flip-flop device, a clock buffer, and so on. Since the number of the electronic components is large, some problems occur. When the CDR circuit 100 is operated in the normal mode, the energy consumed by the high speed phase detector 110 is appropriately 70% of the energy consumed by the whole CDR circuit 100.
Generally, when the operation mode of the conventional CDR circuit 100 is switched from the power off mode, the locking time exceeds 20 μs. For example, in the L0s or L1 state of the PCIe field, the conventional CDR circuit 100 has to be operated in the power-saving mode with the low latency. Consequently, the CDR circuit 100 cannot enter the power off mode.
For meeting the requirement of the low latency, the conventional CDR circuit 100 is almost fully turned on in the power-saving mode, and the conventional CDR circuit 100 works in the like-normal mode. That is, although the CDR circuit 100 is in the power-saving mode, the high speed phase detector 110 still works. Consequently, the power consumption of the CDR circuit 100 is very high.